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1.35v ddr3l sdram udimm mt8ktf12864az C 1gb mt8ktf25664az C 2gb MT8KTF51264AZ C 4gb features ? ddr3l functionality and operations supported as defined in the component data sheet ? 240-pin, unbuffered dual in-line memory module (udimm) ? fast data transfer rates: pc3-14900, pc3-12800, or pc3-10600 ? 1gb (128 meg x 64), 2gb (256 meg x 64), or 4gb (512 meg x 64) ? v dd = v ddq = 1.35v (1.238C1.45v) ? v dd = v ddq = 1.5v (1.425C1.575v) ? backward-compatible to v dd = v ddq = 1.5v 0.075v ? v ddspd = 3.0C3.6v ? reset pin for improved system stability ? nominal and dynamic on-die termination (odt) for data, strobe, and mask signals ? single-rank ? fixed burst chop (bc) of 4 and burst length (bl) of 8 via the mode register set (mrs) ? adjustable data-output drive strength ? serial presence-detect (spd) eeprom ? gold edge contacts ? halogen-free ? fly-by topology ? terminated control, command, and address bus figure 1: 240-pin udimm (mo-269 r/c-a) module height: 30mm (1.181in) figure 2: 240-pin udimm (mo-269 r/c-a1) module height: 30.0mm (1.181in) options marking ? operating temperature C commercial (0c t a 70c) none ? package C 240-pin dimm (halogen-free) z ? frequency/cas latency C 1.07ns @ cl = 13 (ddr3-1866) -1g9 C 1.25ns @ cl = 11 (ddr3-1600) -1g6 C 1.5ns @ cl = 9 (ddr3-1333) -1g4 table 1: key timing parameters speed grade industry nomenclature data rate (mt/s) t rcd (ns) t rp (ns) t rc (ns) cl = 13 cl = 11 cl = 10 cl = 9 cl = 8 cl = 7 cl = 6 cl = 5 -1g9 pc3-14900 1866 1600 1333 1333 1066 1066 800 667 13.125 13.125 47.125 -1g6 pc3-12800 C 1600 1333 1333 1066 1066 800 667 13.125 13.125 48.125 -1g4 pc3-10600 C C 1333 1333 1066 1066 800 667 13.125 13.125 49.125 -1g1 pc3-8500 C C C C 1066 1066 800 667 13.125 13.125 50.625 -1g0 pc3-8500 C C C C 1066 C 800 667 15 15 52.5 -80b pc3-6400 C C C C C C 800 667 15 15 52.5 1gb, 2gb, 4gb (x64, sr) 240-pin 1.35v ddr3l udimm features pdf: 09005aef8413b5fe ktf8c128_256_512x64az.pdf C rev. k 9/15 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice.
table 2: addressing parameter 1gb 2gb 4gb refresh count 8k 8k 8k row address 16k a[13:0] 32k a[14:0] 64k a[15:0] device bank address 8 ba[2:0] 8 ba[2:0] 8 ba[2:0] device configuration 1gb (128 meg x 8) 2gb (256 meg x 8) 4gb (512 meg x 8) column address 1k a[9:0] 1k a[9:0] 1k a[9:0] module rank address 1 s0# 1 s0# 1 s0# table 3: part numbers and timing parameters C 1gb modules base device: mt41k128m8, 1 1gb ddr3l sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt8ktf12864az-1g6__ 1gb 128 meg x 64 12.8 gb/s 1.25ns/1600 mt/s 11-11-11 mt8ktf12864az-1g4__ 1gb 128 meg x 64 10.6 gb/s 1.5ns/1333 mt/s 9-9-9 table 4: part numbers and timing parameters C 2gb modules base device: mt41k256m8, 1 2gb ddr3l sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt8ktf25664az-1g6__ 2gb 256 meg x 64 12.8 gb/s 1.25ns/1600 mt/s 11-11-11 mt8ktf25664az-1g4__ 2gb 256 meg x 64 10.6 gb/s 1.5ns/1333 mt/s 9-9-9 table 5: part numbers and timing parameters C 4gb modules base device: mt41k512m8, 1 4gb ddr3l sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) MT8KTF51264AZ-1g9__ 4gb 512 meg x 64 14.9 gb/s 1.07ns/1866 mt/s 13-13-13 MT8KTF51264AZ-1g6__ 4gb 512 meg x 64 12.8 gb/s 1.25ns/1600 mt/s 11-11-11 notes: 1. data sheets for the base device parts can be found on microns web site. 2. all part numbers end with a two-place code (not shown) that designates component and pcb revisions. consult factory for current revision codes. example: MT8KTF51264AZ-1g9 p1. 1gb, 2gb, 4gb (x64, sr) 240-pin 1.35v ddr3l udimm features pdf: 09005aef8413b5fe ktf8c128_256_512x64az.pdf C rev. k 9/15 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved.
pin assignments table 6: pin assignments 240-pin ddr3 udimm front 240-pin ddr3 udimm back pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1 v refdq 31 dq25 61 a2 91 dq41 121 v ss 151 v ss 181 a1 211 v ss 2 v ss 32 v ss 62 v dd 92 v ss 122 dq4 152 dm3 182 v dd 212 dm5 3 dq0 33 dqs3# 63 nf 93 dqs5# 123 dq5 153 nc 183 v dd 213 nc 4 dq1 34 dqs3 64 nf 94 dqs5 124 v ss 154 v ss 184 ck0 214 v ss 5 v ss 35 v ss 65 v dd 95 v ss 125 dm0 155 dq30 185 ck0# 215 dq46 6 dqs0# 36 dq26 66 v dd 96 dq42 126 nc 156 dq31 186 v dd 216 dq47 7 dqs0 37 dq27 67 v refca 97 dq43 127 v ss 157 v ss 187 nc 217 v ss 8 v ss 38 v ss 68 nc 98 v ss 128 dq6 158 nc 188 a0 218 dq52 9 dq2 39 nc 69 v dd 99 dq48 129 dq7 159 nc 189 v dd 219 dq53 10 dq3 40 nc 70 a10 100 dq49 130 v ss 160 v ss 190 ba1 220 v ss 11 v ss 41 v ss 71 ba0 101 v ss 131 dq12 161 nc 191 v dd 221 dm6 12 dq8 42 nc 72 v dd 102 dqs6# 132 dq13 162 nc 192 ras# 222 nc 13 dq9 43 nc 73 we# 103 dqs6 133 v ss 163 v ss 193 s0# 223 v ss 14 v ss 44 v ss 74 cas# 104 v ss 134 dm1 164 nc 194 v dd 224 dq54 15 dqs1# 45 nc 75 v dd 105 dq50 135 nc 165 nc 195 odt0 225 dq55 16 dqs1 46 nc 76 nc 106 dq51 136 v ss 166 v ss 196 a13 226 v ss 17 v ss 47 v ss 77 nc 107 v ss 137 dq14 167 nc 197 v dd 227 dq60 18 dq10 48 nc 78 v dd 108 dq56 138 dq15 168 reset# 198 nc 228 dq61 19 dq11 49 nc 79 nc 109 dq57 139 v ss 169 nc 199 v ss 229 v ss 20 v ss 50 cke0 80 v ss 110 v ss 140 dq20 170 v dd 200 dq36 230 dm7 21 dq16 51 v dd 81 dq32 111 dqs7# 141 dq21 171 nf/a15 1 201 dq37 231 nc 22 dq17 52 ba2 82 dq33 112 dqs7 142 v ss 172 nf/a14 2 202 v ss 232 v ss 23 v ss 53 nc 83 v ss 113 v ss 143 dm2 173 v dd 203 dm4 233 dq62 24 dqs2# 54 v dd 84 dqs4# 114 dq58 144 nc 174 a12 204 nc 234 dq63 25 dqs2 55 a11 85 dqs4 115 dq59 145 v ss 175 a9 205 v ss 235 v ss 26 v ss 56 a7 86 v ss 116 v ss 146 dq22 176 v dd 206 dq38 236 v ddspd 27 dq18 57 v dd 87 dq34 117 sa0 147 dq23 177 a8 207 dq39 237 sa1 28 dq19 58 a5 88 dq35 118 scl 148 v ss 178 a6 208 v ss 238 sda 29 v ss 59 a4 89 v ss 119 sa2 149 dq28 179 v dd 209 dq44 239 v ss 30 dq24 60 v dd 90 dq40 120 v tt 150 dq29 180 a3 210 dq45 240 v tt notes: 1. pin 171 is nf for 1gb and 2gb; a14 for 4gb. 2. pin 172 is nf for 1gb; a14 for 2gb and 4gb. 1gb, 2gb, 4gb (x64, sr) 240-pin 1.35v ddr3l udimm pin assignments pdf: 09005aef8413b5fe ktf8c128_256_512x64az.pdf C rev. k 9/15 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved.
pin descriptions the pin description table below is a comprehensive list of all possible pins for all ddr3 modules. all pins listed may not be supported on this module. see pin assignments for information specific to this module. table 7: pin descriptions symbol type description ax input address inputs: provide the row address for active commands, and the column ad- dress and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge command determines whether the precharge applies to one bank (a10 low, bank selected by bax) or all banks (a10 high). the address inputs also provide the op-code during a load mode command. see the pin assignments table for density-specific ad- dressing information. bax input bank address inputs: define the device bank to which an active, read, write, or precharge command is being applied. ba define which mode register (mr0, mr1, mr2, or mr3) is loaded during the load mode command. ckx, ckx# input clock: differential clock inputs. all control, command, and address input signals are sampled on the crossing of the positive edge of ck and the negative edge of ck#. ckex input clock enable: enables (registered high) and disables (registered low) internal circui- try and clocks on the dram. dmx input data mask (x8 devices only): dm is an input mask signal for write data. input data is masked when dm is sampled high, along with that input data, during a write ac- cess. although dm pins are input-only, dm loading is designed to match that of the dq and dqs pins. odtx input on-die termination: enables (registered high) and disables (registered low) termi- nation resistance internal to the ddr3 sdram. when enabled in normal operation, odt is only applied to the following pins: dq, dqs, dqs#, dm, and cb. the odt input will be ignored if disabled via the load mode command. par_in input parity input: parity bit for ax, ras#, cas#, and we#. ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with s#) define the command being entered. reset# input (lvcmos) reset: reset# is an active low asychronous input that is connected to each dram and the registering clock driver. after reset# goes high, the dram must be reinitial- ized as though a normal power-up was executed. sx# input chip select: enables (registered low) and disables (registered high) the command decoder. sax input serial address inputs: used to configure the temperature sensor/spd eeprom ad- dress range on the i 2 c bus. scl input serial clock for temperature sensor/spd eeprom: used to synchronize communi- cation to and from the temperature sensor/spd eeprom on the i 2 c bus. cbx i/o check bits: used for system error detection and correction. dqx i/o data input/output: bidirectional data bus. dqsx, dqsx# i/o data strobe: differential data strobes. output with read data; edge-aligned with read data; input with write data; center-aligned with write data. 1gb, 2gb, 4gb (x64, sr) 240-pin 1.35v ddr3l udimm pin descriptions pdf: 09005aef8413b5fe ktf8c128_256_512x64az.pdf C rev. k 9/15 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved.
table 7: pin descriptions (continued) symbol type description sda i/o serial data: used to transfer addresses and data into and out of the temperature sen- sor/spd eeprom on the i 2 c bus. tdqsx, tdqsx# output redundant data strobe (x8 devices only): tdqs is enabled/disabled via the load mode command to the extended mode register (emr). when tdqs is enabled, dm is disabled and tdqs and tdqs# provide termination resistance; otherwise, tdqs# are no function. err_out# output (open drain) parity error output: parity error found on the command and address bus. event# output (open drain) temperature event: the event# pin is asserted by the temperature sensor when crit- ical temperature thresholds have been exceeded. v dd supply power supply: 1.35v (1.283C1.45v) backward-compatible to 1.5v (1.425C1.575v). the component v dd and v ddq are connected to the module v dd . v ddspd supply temperature sensor/spd eeprom power supply: 3.0C3.6v. v refca supply reference voltage: control, command, and address v dd /2. v refdq supply reference voltage: dq, dm v dd /2. v ss supply ground. v tt supply termination voltage: used for control, command, and address v dd /2. nc C no connect: these pins are not connected on the module. nf C no function: these pins are connected within the module, but provide no functional- ity. 1gb, 2gb, 4gb (x64, sr) 240-pin 1.35v ddr3l udimm pin descriptions pdf: 09005aef8413b5fe ktf8c128_256_512x64az.pdf C rev. k 9/15 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved.
dq map table 8: component-to-module dq map component reference number component dq module dq module pin number component reference number component dq module dq module pin number u1 0 7 129 u2 0 15 138 1 5 123 1 13 132 2 6 128 2 14 137 3 0 3 3 8 12 4 3 10 4 11 19 5 4 122 5 12 131 6 2 9 6 10 18 7 1 4 7 9 13 u3 0 23 147 u4 0 31 156 1 21 141 1 29 150 2 22 146 2 30 155 3 16 21 3 24 30 4 19 28 4 27 37 5 20 140 5 28 149 6 18 27 6 26 36 7 17 22 7 25 31 u5 0 39 207 u6 0 47 216 1 37 201 1 45 210 2 38 206 2 46 215 3 32 81 3 40 90 4 35 88 4 43 97 5 36 200 5 44 209 6 34 87 6 42 96 7 33 82 7 41 91 u7 0 55 225 u8 0 63 234 1 53 219 1 61 228 2 54 224 2 62 233 3 48 99 3 56 108 4 51 106 4 59 115 5 52 218 5 60 227 6 50 105 6 58 114 7 49 100 7 57 109 1gb, 2gb, 4gb (x64, sr) 240-pin 1.35v ddr3l udimm dq map pdf: 09005aef8413b5fe ktf8c128_256_512x64az.pdf C rev. k 9/15 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved.
functional block diagram figure 3: functional block diagram dq dq dq dq dq dq dq dq zq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u1 dm cs# dqs dqs# dq dq dq dq dq dq dq dq zq dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 u5 dm cs# dqs dqs# dq dq dq dq dq dq dq dq zq dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 u2 dm cs# dqs dqs# dq dq dq dq dq dq dq dq zq dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 u3 dm cs# dqs dqs# dq dq dq dq dq dq dq dq zq dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 u4 dm cs# dqs dqs# dq dq dq dq dq dq dq dq zq dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 u6 dm cs# dqs dqs# dq dq dq dq dq dq dq dq zq dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 u7 dm cs# dqs dqs# dq dq dq dq dq dq dq dq zq dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 u8 dm cs# dqs dqs# dqs0# dqs0 dm0 s0# dqs1# dqs1 dm1 dqs2# dqs2 dm2 dqs3# dqs3 dm3 dqs4# dqs4 dm4 dqs5# dqs5 dm5 dqs6# dqs6 dm6 dqs7# dqs7 dm7 ba[2:0] a[15/14/13:0] ras# cas# we# cke0 odt0 reset# ba[2:0]: ddr3 sdram a[15/14/13:0]: ddr3 sdram ras#: ddr3 sdram cas#: ddr3 sdram we#: ddr3 sdram cke0: ddr3 sdram odt0: ddr3 sdram reset#: ddr3 sdram ddr3 sdram x8 ck0 ck0# a0 spd eeprom a1 a2 sa0 sa1 sda scl wp u9 v refca v ss ddr3 sdram ddr3 sdram v dd address, command, and control termination v ddspd spd eeprom v tt ddr3 sdram ddr3 sdram v refdq v ss address, command, control, and clock line terminations: cke0, a[15/14/13:0], ras#, cas#, we#, s0#, odt0, ba[2:0] ck0 ck0# sa2 v ss v ss v ss v ss v ss v ss v ss v ss ddr3 sdram v tt ddr3 sdram v dd ck1 ck1# unused clock termination note: 1. the zq ball on each ddr3 component is connected to an external 240 1% resistor that is tied to ground. it is used for the calibration of the components odt and output driver. 1gb, 2gb, 4gb (x64, sr) 240-pin 1.35v ddr3l udimm functional block diagram pdf: 09005aef8413b5fe ktf8c128_256_512x64az.pdf C rev. k 9/15 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved.
general description ddr3 sdram modules are high-speed, cmos dynamic random access memory mod- ules that use internally configured 8-bank ddr3 sdram devices. ddr3 sdram mod- ules use ddr architecture to achieve high-speed operation. ddr3 architecture is essen- tially an 8 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr3 sdram mod- ule effectively consists of a single 8 n -bit-wide, one-clock-cycle data transfer at the inter- nal dram core and eight corresponding n -bit-wide, one-half-clock-cycle data transfers at the i/o pins. ddr3 modules use two sets of differential signals: dqs, dqs# to capture data and ck and ck# to capture commands, addresses, and control signals. differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals. fly-by topology ddr3 modules use faster clock speeds than earlier ddr technologies, making signal quality more important than ever. for improved signal quality, the clock, control, com- mand, and address buses have been routed in a fly-by topology, where each clock, con- trol, command, and address pin on each dram is connected to a single trace and ter- minated (rather than a tree structure, where the termination is off the module near the connector). inherent to fly-by topology, the timing skew between the clock and dqs sig- nals can be easily accounted for by using the write-leveling feature of ddr3. serial presence-detect eeprom operation ddr3 sdram modules incorporate serial presence-detect. the spd data is stored in a 256-byte eeprom. the first 128 bytes are programmed by micron to comply with jedec standard jc-45, "appendix x: serial presence detect (spd) for ddr3 sdram modules." these bytes identify module-specific timing parameters, configuration infor- mation, and physical attributes. the remaining 128 bytes of storage are available for use by the customer. system read/write operations between the master (system logic) and the slave eeprom device occur via a standard i 2 c bus using the dimms scl (clock) sda (data), and sa (address) pins. write protect (wp) is connected to v ss , per- manently disabling hardware write protection. for further information refer to micron technical note tn-04-42, "memory module serial presence-detect." 1gb, 2gb, 4gb (x64, sr) 240-pin 1.35v ddr3l udimm general description pdf: 09005aef8413b5fe ktf8c128_256_512x64az.pdf C rev. k 9/15 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved.
electrical specifications stresses greater than those listed may cause permanent damage to the module. this is a stress rating only, and functional operation of the module at these or any other condi- tions outside those indicated in each device's data sheet is not implied. exposure to ab- solute maximum rating conditions for extended periods may adversely affect reliability. table 9: absolute maximum ratings symbol parameter min max units v dd v dd supply voltage relative to v ss C0.4 1.975 v v in , v out voltage on any pin relative to v ss C0.4 1.975 v table 10: operating conditions symbol parameter min nom max units notes v dd v dd supply voltage 1.283 1.35 1.45 v 1.425 1.5 1.575 v 1 i vtt termination reference current from v tt C600 C 600 ma v tt termination reference voltage (dc) C command/address bus 0.49 v dd - 20mv 0.5 v dd 0.51 v dd + 20mv v 2 i i input leakage current; any input 0v v in v dd ; v ref input 0v v in 0.95v (all other pins not under test = 0v) address in- puts, ras#, cas#, we#, ba, s#, cke, odt, ck, ck# C16 0 16 a dm C2 0 2 i oz output leakage current; 0v v out v ddq ; dq and odt are disabled; odt is high dq, dqs, dqs# C5 0 5 a i vref v ref supply leakage current; v refdq = v dd /2 or v refca = v dd /2 (all other pins not under test = 0v.) C8 0 8 a t a module ambient operating temperature commercial 0 C 70 c 3, 4 t c ddr3 sdram component case operating temperature commercial 0 C 95 c 3, 4, 5 notes: 1. module is backward-compatible with 1.5v operation. refer to device specification for details and operation guidance. 2. v tt termination voltage in excess of the stated limit will adversely affect the command and address signals voltage margin and will reduce timing margins. 3. t a and t c are simultaneous requirements. 4. for further information, refer to technical note tn-00-08: thermal applications, avail- able on microns web site. 5. the refresh rate is required to double when 85c < t c 95c. 1gb, 2gb, 4gb (x64, sr) 240-pin 1.35v ddr3l udimm electrical specifications pdf: 09005aef8413b5fe ktf8c128_256_512x64az.pdf C rev. k 9/15 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved.
dram operating conditions recommended ac operating conditions are given in the ddr3 component data sheets. component specifications are available at micron.com . module speed grades correlate with component speed grades, as shown below. table 11: module and component speed grades ddr3 components may exceed the listed module speed grades; module may not be available in all listed speed grades module speed grade component speed grade -2g1 -093 -1g9 -107 -1g6 -125 -1g4 -15e -1g1 -187e -1g0 -187 -80c -25e -80b -25 design considerations simulations micron memory modules are designed to optimize signal integrity through carefully de- signed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. however, good signal integrity starts at the system level. micron encourages designers to simulate the signal characteristics of the system's memory bus to ensure adequate signal integrity of the entire memory system. power operating voltages are specified at the dram, not at the edge connector of the module. designers must account for any system voltage drops at anticipated power levels to en- sure the required supply voltage is maintained. 1gb, 2gb, 4gb (x64, sr) 240-pin 1.35v ddr3l udimm dram operating conditions pdf: 09005aef8413b5fe ktf8c128_256_512x64az.pdf C rev. k 9/15 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved.
i dd specifications table 12: ddr3 i dd specifications and conditions C 1gb (die revision j) values are for the mt41k128m8 ddr3l sdram only and are computed from values specified in the 1gb (128 meg x 8) component data sheet parameter symbol 1600 1333 units operating current 0: one bank activate-to-precharge i dd0 272 264 ma operating current 1: one bank activate-to-read-to-precharge i dd1 360 344 ma precharge power-down current: slow exit i dd2p0 96 96 ma precharge power-down current: fast exit i dd2p1 96 96 ma precharge quiet standby current i dd2q 120 120 ma precharge standby current i dd2n 136 136 ma precharge standby odt current i dd2nt 200 192 ma active power-down current i dd3p 112 112 ma active standby current i dd3n 192 184 ma burst read operating current i dd4r 664 576 ma burst write operating current i dd4w 704 616 ma refresh current i dd5b 1280 1240 ma self refresh temperature current: max t c = 85c i dd6 96 96 ma self refresh temperature current (srt-enabled): max t c = 95c i dd6et 112 112 ma all banks interleaved read current i dd7 1192 1152 ma reset current i dd8 112 112 ma 1gb, 2gb, 4gb (x64, sr) 240-pin 1.35v ddr3l udimm i dd specifications pdf: 09005aef8413b5fe ktf8c128_256_512x64az.pdf C rev. k 9/15 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved.
table 13: ddr3 i dd specifications and conditions C 2gb (die revision k) values are for the mt41k256m8 ddr3l sdram only and are computed from values specified in the 2gb (256 meg x 8) component data sheet parameter symbol 1600 1333 units operating current 0: one bank activate-to-precharge i dd0 312 304 ma operating current 1: one bank activate-to-read-to-precharge i dd1 416 400 ma precharge power-down current: slow exit i dd2p0 96 96 ma precharge power-down current: fast exit i dd2p1 112 112 ma precharge quiet standby current i dd2q 160 160 ma precharge standby current i dd2n 168 168 ma precharge standby odt current i dd2nt 248 232 ma active power-down current i dd3p 168 168 ma active standby current i dd3n 256 240 ma burst read operating current i dd4r 752 656 ma burst write operating current i dd4w 776 680 ma refresh current i dd5b 1440 1432 ma self refresh temperature current: max t c = 85c i dd6 96 96 ma self refresh temperature current (srt-enabled): max t c = 95c i dd6et 120 120 ma all banks interleaved read current i dd7 1248 1200 ma reset current i dd8 112 112 ma 1gb, 2gb, 4gb (x64, sr) 240-pin 1.35v ddr3l udimm i dd specifications pdf: 09005aef8413b5fe ktf8c128_256_512x64az.pdf C rev. k 9/15 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved.
table 14: ddr3 i dd specifications and conditions C 4gb (die revision e) values are for the mt41k512m8 ddr3l sdram only and are computed from values specified in the 4gb (512 meg x 8) component data sheet parameter symbol 1866 1600 units operating current 0: one bank activate-to-precharge i dd0 496 440 ma operating current 1: one bank activate-to-read-to-precharge i dd1 560 528 ma precharge power-down current: slow exit i dd2p0 144 144 ma precharge power-down current: fast exit i dd2p1 296 256 ma precharge quiet standby current i dd2q 280 256 ma precharge standby current i dd2n 280 256 ma precharge standby odt current i dd2nt 336 312 ma active power-down current i dd3p 328 304 ma active standby current i dd3n 328 304 ma burst read operating current i dd4r 1392 1256 ma burst write operating current i dd4w 1128 1000 ma refresh current i dd5b 1936 1880 ma self refresh temperature current: max t c = 85c i dd6 160 160 ma self refresh temperature current (srt-enabled): max t c = 95c i dd6et 200 200 ma all banks interleaved read current i dd7 2008 1760 ma reset current i dd8 160 160 ma 1gb, 2gb, 4gb (x64, sr) 240-pin 1.35v ddr3l udimm i dd specifications pdf: 09005aef8413b5fe ktf8c128_256_512x64az.pdf C rev. k 9/15 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved.
table 15: ddr3 i dd specifications and conditions C 4gb (die revision n) values are for the mt41k512m8 ddr3l sdram only and are computed from values specified in the 4gb (512 meg x 8) component data sheet parameter symbol 1866 1600 units operating current 0: one bank activate-to-precharge i dd0 392 376 ma operating current 1: one bank activate-to-read-to-precharge i dd1 512 488 ma precharge power-down current: slow exit i dd2p0 64 64 ma precharge power-down current: fast exit i dd2p1 128 112 ma precharge quiet standby current i dd2q 208 192 ma precharge standby current i dd2n 208 192 ma precharge standby odt current i dd2nt 240 224 ma active power-down current i dd3p 224 208 ma active standby current i dd3n 256 240 ma burst read operating current i dd4r 840 760 ma burst write operating current i dd4w 840 760 ma refresh current i dd5b 1440 1400 ma self refresh temperature current: max t c = 85c i dd6 96 96 ma self refresh temperature current (srt-enabled): max t c = 95c i dd6et 128 128 ma all banks interleaved read current i dd7 1120 1040 ma reset current i dd8 80 80 ma 1gb, 2gb, 4gb (x64, sr) 240-pin 1.35v ddr3l udimm i dd specifications pdf: 09005aef8413b5fe ktf8c128_256_512x64az.pdf C rev. k 9/15 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved.
table 16: ddr3 i dd specifications and conditions C 4gb (die revision p) values are for the mt41k512m8 ddr3l sdram only and are computed from values specified in the 4gb (512 meg x 8) component data sheet parameter symbol 1866 1600 units operating current 0: one bank activate-to-precharge i dd0 232 224 ma operating current 1: one bank activate-to-read-to-precharge i dd1 352 344 ma precharge power-down current: slow exit i dd2p0 88 80 ma precharge power-down current: fast exit i dd2p1 88 88 ma precharge quiet standby current i dd2q 120 120 ma precharge standby current i dd2n 136 128 ma precharge standby odt current i dd2nt 176 160 ma active power-down current i dd3p 120 120 ma active standby current i dd3n 168 160 ma burst read operating current i dd4r 816 720 ma burst write operating current i dd4w 904 808 ma refresh current i dd5b 1216 1216 ma self refresh temperature current: max t c = 85c i dd6 120 120 ma self refresh temperature current (srt-enabled): max t c = 95c i dd6et 184 184 ma all banks interleaved read current i dd7 1168 1040 ma reset current i dd8 104 104 ma 1gb, 2gb, 4gb (x64, sr) 240-pin 1.35v ddr3l udimm i dd specifications pdf: 09005aef8413b5fe ktf8c128_256_512x64az.pdf C rev. k 9/15 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved.
serial presence-detect eeprom for the latest spd data, refer to micron's spd page: micron.com/spd . table 17: serial presence-detect eeprom dc operating conditions all voltages referenced to v ddspd parameter/condition symbol min max units supply voltage v ddspd 3.0 3.6 v input low voltage: logic 0; all inputs v il C0.45 v ddspd x 0.3 v input high voltage: logic 1; all inputs v ih v ddspd x 0.7 v ddspd + 1.0 v output low voltage: i out = 3ma v ol C 0.4 v input leakage current: v in = gnd to v dd i li 0.1 2.0 a output leakage current: v out = gnd to v dd i lo 0.05 2.0 a table 18: serial presence-detect eeprom ac operating conditions parameter/condition symbol min max units notes clock frequency t scl 10 400 khz clock pulse width high time t high 0.6 C s clock pulse width low time t low 1.3 C s sda rise time t r C 300 s 1 sda fall time t f 20 300 ns 1 data-in setup time t su:dat 100 C ns data-in hold time t hd:di 0 C s data-out hold time t hd:dat 200 900 ns data out access time from scl low t aa:dat 0.2 0.9 s 2 start condition setup time t su:sta 0.6 C s 3 start condition hold time t hd:sta 0.6 C s stop condition setup time t su:sto 0.6 C s time the bus must be free before a new transition can start t buf 1.3 C s write time t w C 10 ms notes: 1. guaranteed by design and characterization, not necessarily tested. 2. to avoid spurious start and stop conditions, a minimum delay is placed between the fall- ing edge of scl and the falling or rising edge of sda. 3. for a restart condition, or following a write cycle. 1gb, 2gb, 4gb (x64, sr) 240-pin 1.35v ddr3l udimm serial presence-detect eeprom pdf: 09005aef8413b5fe ktf8c128_256_512x64az.pdf C rev. k 9/15 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved.
module dimensions figure 4: 240-pin ddr3 udimm (r/c-a) 30.50 (1.20) 29.85 (1.175) pin 1 17.3 (0.68) typ 2.50 (0.098) d (2x) 2.30 (0.091) typ 5.0 (0.197) typ 123.0 (4.84) typ 1.0 (0.039) typ 0.80 (0.031) typ 0.75 (0.03) r (8x) 0.76 (0.030) r pin 120 front view 133.50 (5.256) 133.20 (5.244) 47.0 (1.85) typ 71.0 (2.79) typ 9.5 (0.374) typ back view pin 240 pin 121 1.37 (0.054) 1.17 (0.046) 2.7 (0.106) max 2.20 (0.087) typ 1.45 (0.057) typ 3.05 (0.12) typ 54.68 (2.15) typ 3.0 (0.118) 4x typ 23.3 (0.92) typ 0.50 (0.02) r (4x) 0.9 (0.035) typ 1.0 (0.039) r (8x) 15.0 (0.59) 4x typ 3.1 (0.122) 2x typ 5.1 (0.2) typ u1 u2 u3 u4 u9 u5 u6 u7 u8 no components this side of module 45, 4x notes: 1. all dimensions are in millimeters (inches); max/min or typical (typ) where noted. 2. the dimensional diagram is for reference only. refer to the jedec mo document for ad- ditional design dimensions. 1gb, 2gb, 4gb (x64, sr) 240-pin 1.35v ddr3l udimm module dimensions pdf: 09005aef8413b5fe ktf8c128_256_512x64az.pdf C rev. k 9/15 en 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved.
figure 5: 240-pin ddr3 udimm (r/c-a1) 30.50 (1.20) 29.85 (1.175) pin 1 17.3 (0.68) typ 2.50 (0.098) d (2x) 2.30 (0.091) typ 5.0 (0.197) typ 123.0 (4.84) typ 1.0 (0.039) typ 0.80 (0.031) typ 0.75 (0.03) r (8x) 0.76 (0.030) r pin 120 front view 133.50 (5.256) 133.20 (5.244) 47.0 (1.85) typ 71.0 (2.79) typ 9.5 (0.374) typ back view pin 240 pin 121 1.37 (0.054) 1.17 (0.046) 2.7 (0.106) max 2.20 (0.087) typ 1.45 (0.057) typ 3.05 (0.12) typ 54.68 (2.15) typ 3.0 (0.118) x4 typ 0.6 (0.024) x 45 (4x) u1 u2 u3 u4 u9 u5 u6 u7 u8 no components this side of module notes: 1. all dimensions are in millimeters (inches); max/min or typical (typ) where noted. 2. the dimensional diagram is for reference only. refer to the jedec mo document for ad- ditional design dimensions. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-4000 www.micron.com/products/support sales inquiries: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 1gb, 2gb, 4gb (x64, sr) 240-pin 1.35v ddr3l udimm module dimensions pdf: 09005aef8413b5fe ktf8c128_256_512x64az.pdf C rev. k 9/15 en 18 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved.

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